A shared bus system generally includes a DATABUS, ADRBUS, and CONTROLBUS, with the operation of the system following a protocol. An address transferred on the ADRBUS selects one of several devices coupled to the bus and the transfer of data between the selected device and the bus is controlled by control signals such as R/W and a system clock.
Most shared bus systems will include a memory such as a Dynamic Random Access Memory (DRAM) to store data. In addition to transferring data to and from the DATABUS the DRAM may have other functions which limit its availability to the BUS system. Thus, the BUS system may be ready to write data to the DRAM when the DRAM is not available
As is well-known in the art, FIFOs are useful for buffering data. By using a FIFO, no data are lost if the DRAM isn't ready to receive each word when the BUS system is ready to transfer.
When data is stored in the FIFO it asserts a request signal (DRAMREQ) that is serviced by the DRAM as soon as it becomes free of other duties. If the FIFO write clock is based on the bus protocol and the FIFO read clock is based on RAM availability, then the FIFO will be read whenever one word of data is stored if the read clock is faster than the write clock. However, transferring one level of data from the FIFO to the DRAM does not take advantage of the increased transfer rate available if the page mode of the DRAM is utilized. For the transfer of a single word, the time for servicing a DRAMREQ is equal to the non-page mode access time of the DRAM and the system operates at a slow rate.